DocumentCode :
3212069
Title :
Issues in fault modelling and testing of micropipelines
Author :
Pagey, Sandeep ; Sherlekar, S.D. ; Venkatesh, G.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
fYear :
1992
fDate :
26-27 Nov 1992
Firstpage :
107
Lastpage :
111
Abstract :
Micropipelines, suggested by Ivan Sutherland (1989) form an elegant scheme for asynchronous implementation of pipelined circuits. The authors analyse the faulty behavior of micropipelines and propose schemes for testing. They suggest that the control part of the micropipeline is concurrently testable during normal operation and that test pattern generation for the data part logic can be reduced to that for combinational circuits, with a simple modification only in the test application method. Testing latches require a two-pattern test which can be generated using test pattern generation techniques for combinational circuits
Keywords :
combinatorial circuits; computer testing; fault location; logic testing; pipeline processing; protocols; C-element; asynchronous implementation; asynchronous protocols; combinational circuits; fault modelling; logic testing; micropipelines; pipelined circuits; test pattern generation; two-pattern test; Circuit faults; Circuit testing; Combinational circuits; Delay; Latches; Logic circuits; Logic testing; Pipelines; Switches; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)
Conference_Location :
Hiroshima
Print_ISBN :
0-8186-2985-1
Type :
conf
DOI :
10.1109/ATS.1992.224446
Filename :
224446
Link To Document :
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