An FPGA Implementation of the Distributed Arithmetic Based Quaternionic Multipliers for Paraunitary Filter Banks

If a digital paraunitary filter bank (PUFB) designed using hypercomplex number theory is to be implemented in hardware, the throughput and chip area of used quaternion multipliers are of critical importance. In this paper, digit (L-bit)-serial quaternion multipliers based on the distributed arithmetic are presented as circuits well suited for FPGA-based fixed-point implementations of PUFBs. Apart from a theoretical development, experimental design results obtained using a Xilinx Virtex FPGA are reported.