DocumentCode
3212173
Title
Non-intrusive design of concurrently self-testable FSMs
Author
Drineas, Petros ; Makris, Yiorgos
Author_Institution
Dept. of Comput. Sci. & Electr. Eng., Yale Univ., New Haven, CT, USA
fYear
2002
fDate
18-20 Nov. 2002
Firstpage
33
Lastpage
38
Abstract
We propose a methodology for the non-intrusive design of concurrently self-testable FSMs. The proposed method is similar to duplication, wherein a replica of the original FSM acts as a predictor that immediately detects potential faults by comparison to the original FSM. However, instead of duplicating the complete FSM, the proposed method replicates only a minimal portion adequate to detect all possible faults, yet at the cost of introducing potential fault detection latency. Furthermore, in contrast to concurrent error detection approaches, which presume the ability to re-synthesize the FSM and exploit parity-based state encoding, the proposed method is non-intrusive and does not interfere with the encoding and implementation of the original FSM. Experimental results on FSMs of various sizes and densities indicate that the proposed method detects 100% of the faults with very low average fault detection latency. Furthermore, a hardware overhead reduction of up to 33% is achieved, as compared to duplication-based concurrent error detection.
Keywords
automatic test pattern generation; error detection; finite state machines; logic circuits; logic design; logic testing; ATPG; concurrently self-testable FSM; duplication; fault detection latency; hardware overhead reduction; nonintrusive design methodology; parity-based state encoding; Built-in self-test; Circuit faults; Circuit testing; Costs; Delay; Design methodology; Electrical fault detection; Encoding; Fault detection; Hardware;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
ISSN
1081-7735
Print_ISBN
0-7695-1825-7
Type
conf
DOI
10.1109/ATS.2002.1181681
Filename
1181681
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