DocumentCode
3212226
Title
MinMux: a new approach for global minimization of multiplexers in interconnect synthesis
Author
Wilson, T.C. ; Garg, M.K. ; Deadman, R. ; Halley, B. ; Banerji, D.K.
Author_Institution
Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
fYear
1993
fDate
5-6 Mar 1993
Firstpage
132
Lastpage
138
Abstract
The problem of minimizing interconnection complexity in behavioral level synthesis is considered. In particular, it is assumed that logical connection requirements have already been determined, with a corresponding level of multiplexing implied. The total amount of multiplexing is further reduced by combining connections onto shared path segments, when possible. Using the number of equivalent 2×1 multiplexers as the measure of interconnection complexity, the optimum solution to this problem can be guaranteed. The solution technique uses integer linear programming, preceded by a process that reduces the problem space without compromising optimality. It is shown how to minimize the total number of tristate buffers in a bus implementation
Keywords
circuit layout CAD; integer programming; linear programming; logic CAD; minimisation of switching nets; behavioral level synthesis; bus implementation; global minimization; integer linear programming; interconnect synthesis; multiplexers; tristate buffers; Application specific integrated circuits; Costs; Integrated circuit interconnections; Iterative algorithms; Iterative methods; Merging; Multiplexing; Scheduling; Very large scale integration; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-3430-8
Type
conf
DOI
10.1109/GLSV.1993.224463
Filename
224463
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