DocumentCode
3212234
Title
Seven subthreshold flip-flop cells
Author
Alstad, Håvard Pedersen ; Aunet, Snorre
Author_Institution
Univ. of Oslo, Oslo
fYear
2007
fDate
19-20 Nov. 2007
Firstpage
1
Lastpage
4
Abstract
For ultra-low-power applications, operating the transistors in their subthreshold region is an effective way of reducing the power dissipation of a circuit. This paper presents a comparative study of the performance of seven D-flip-flop cells operating in the subthreshold region, based on simulations in a 90 nm CMOS technology. Simulations have been performed with a supply voltage ranging from 150 mV to 350 mV. The best PDP and EDP numbers at 175 mV is 13 aJ and 10 yJs, respectively.
Keywords
CMOS digital integrated circuits; flip-flops; CMOS technology; flip-flop cells; power dissipation; size 90 nm; subthreshold region; ultra-low-power applications; voltage 150 mV to 350 mV; CMOS technology; Circuit simulation; Clocks; Delay effects; Flip-flops; Informatics; Leakage current; Power dissipation; Power supplies; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Norchip, 2007
Conference_Location
Aalborg
Print_ISBN
978-1-4244-1516-8
Electronic_ISBN
978-1-4244-1517-5
Type
conf
DOI
10.1109/NORCHP.2007.4481061
Filename
4481061
Link To Document