DocumentCode
3212263
Title
Optimizing carry lookahead adders for semicustom CMOS
Author
Thomborson, C.D. ; Sun, Y.
Author_Institution
Dept. of Comput. Sci., Minnesota Univ., Duluth, MN, USA
fYear
1993
fDate
5-6 Mar 1993
Firstpage
119
Lastpage
122
Abstract
The authors present a practical method for constructing optimal carry lookahead adders, of width n ⩽84. They formulate this design problem as a two-dimensional dynamic program, in which optimization is performed with respect to both adder size and latency. The adders are fast, are modularly built, are relatively easy to lay out, and fully exploit the timing characteristics of CMOS standard cells or gate arrays
Keywords
CMOS integrated circuits; adders; application specific integrated circuits; carry logic; circuit CAD; delays; dynamic programming; integrated logic circuits; logic CAD; optimisation; 2D dynamic program; adder size; carry lookahead adders; delay model; gate arrays; latency; optimization; semicustom CMOS; standard cells; timing characteristics; two-dimensional dynamic program; Adders; Binary trees; Circuits; Computer science; Cost function; Delay; Design methodology; Design optimization; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-3430-8
Type
conf
DOI
10.1109/GLSV.1993.224466
Filename
224466
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