Title :
MD-SCAN method for low power scan testing
Author :
Yoshida, Takaki ; Watari, Masafumi
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan
Abstract :
As semiconductor manufacturing technology advances, power dissipation and noise in scan testing have become critical problems. Our studies on practical LSI manufacturing show that power supply voltage drop causes testing problems during shift operations in scan testing. In this paper, we present a new testing method named MD-SCAN (multi duty-scan) which solves power supply voltage drop problems, as well as its experimental results applied to practical LSI chips.
Keywords :
boundary scan testing; electric potential; integrated circuit design; integrated circuit modelling; integrated circuit noise; integrated circuit testing; large scale integration; logic design; logic simulation; logic testing; low-power electronics; LSI manufacturing; MD-SCAN method; low power scan testing; multi duty scan; power supply voltage drop testing problems; scan testing power dissipation/noise; shift operations; Circuit synthesis; Circuit testing; Clocks; Costs; Flip-flops; Large scale integration; Power dissipation; Power supplies; Semiconductor device manufacture; Voltage;
Conference_Titel :
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
Print_ISBN :
0-7695-1825-7
DOI :
10.1109/ATS.2002.1181690
