DocumentCode :
3212334
Title :
Non-scan design for testability based on fault oriented conflict analysis
Author :
Xiang, Dong ; Gu, Shan ; Fujiwara, Hideo
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fYear :
2002
fDate :
18-20 Nov. 2002
Firstpage :
86
Lastpage :
91
Abstract :
A two stage non-scan design for testability method is proposed. The first stage selects test points based on an earlier testability measure conflict. A new testability measure conflict+ based on conflict analysis of hard-faults in the process of test generation is introduced, which emulates most general features of sequential ATPG. A new design for testability algorithm is proposed to select test points by using conflict+. Test points are selected in the second stage based on the hard faults after the initial ATPG run of the design for testability circuit in the preliminary stage. Effective approximation schemes are adopted to get reasonable estimation of the testability measure. Several effective techniques are adopted to accelerate the process of the proposed design for testability algorithm.
Keywords :
automatic test pattern generation; design for testability; fault diagnosis; integrated circuit design; integrated circuit testing; logic design; logic testing; conflict testability measure; fault-oriented conflict analysis; hard-fault conflict analysis; logic testing; nonscan DFT; sequential ATPG; test generation; test point selection; testability measure estimation approximation schemes; two stage nonscan design for testability methods; Design for testability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
ISSN :
1081-7735
Print_ISBN :
0-7695-1825-7
Type :
conf
DOI :
10.1109/ATS.2002.1181691
Filename :
1181691
Link To Document :
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