Specification and design of a new memory fault simulator

Author

Benso, A. ; Di Carlo, S. ; Di Natale, G. ; Prinetto, P.

Author_Institution

Dipt. di Automatica e Informatica, Politecnico di Torino, Italy

fYear

2002

fDate

18-20 Nov. 2002

Firstpage

92

Lastpage

97

Abstract

This paper presents a new fault simulator architecture for RAM memories. The key features of the proposed tool are: (1) user-definable fault models, test algorithm, and memory architecture; (2) very fast simulation algorithm; (3) ability to compute the coverage of any provided test sequence with respect to a user-defined set of fault models, and to eliminate redundant operations; (4) assessment of the power consumption generated by the test application. Moreover, the tool is able to modify the test algorithm in order to guarantee the compliance to user-defined power consumption constraints.

Keywords

circuit simulation; fault simulation; integrated circuit modelling; integrated circuit testing; logic simulation; random-access storage; RAM memories; memory architecture; memory fault simulator architecture; redundant operation elimination; simulator tools; test algorithms; test application power consumption; test sequence fault coverage; user-definable fault models; user-defined power consumption constraints; Analytical models; Computational modeling; Computer architecture; Energy consumption; Memory architecture; Object oriented modeling; Power generation; Random access memory; Read-write memory; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1825-7

Type

conf

DOI

10.1109/ATS.2002.1181693

Filename

1181693