Optimal seed generation for delay fault detection BIST

In delay fault detection BIST (built-in-self-test), an adjacency test pattern generation scheme can generate robust test patterns effectively. Traditional adjacency test pattern generation schemes use an LFSR (linear feedback shift register) to generate initial vectors but they cannot handle circuits with more than 30 inputs. In this paper, a determined BIST scheme, where several seeds are applied, is proposed. Based on analysis of independent partial circuits in the circuit under test, an algorithm is used to generate the seeds - the small number of necessary initial vectors. Through combining outputs of the shift register, the number of shift register stages is reduced. Experiments show that the method of this paper has maximum fault coverage, and short test length that means short lest time. The hardware overhead is at the same level as traditional methods.