Title :
On-chip tap-delay measurements for a digital delay-line used in high-speed inter-chip data communications
Author :
Petre, Octavian ; Kerkhoff, Hans G.
Author_Institution :
Testable Design & Testing of Microsystems Group, MESA+ Res. Inst., Enschede, Netherlands
Abstract :
During the last few years, new synchronization techniques to send data between ICs at increasingly high data-rates have been developed. Some of them rely on digital delay lines. The timing accuracy of the delay lines is crucial for good functionality of the synchronization mechanism. This paper presents a strategy to measure the tap-delays of a digital delay-line, using the well-known oscillation technique. The occurring measurement error for the presented technique has been calculated. Towards the end of the paper, a new delay-line scheme is shown. The tap-delay, measurement becomes much more accurate for this delay-line than for a standard delay-line.
Keywords :
circuit simulation; delay lines; integrated circuit design; integrated circuit modelling; integrated circuit testing; logic design; logic simulation; logic testing; measurement errors; synchronisation; timing circuits; timing jitter; data rates; delay line timing accuracy; digital delay-lines; high-speed inter-chip data communications; measurement errors; on-chip tap-delay measurement; oscillation measurement techniques; synchronization techniques/mechanisms; timing jitter; Circuit testing; Clocks; Data communication; Delay lines; Equations; Power supplies; Propagation delay; Synchronization; Temperature measurement; Timing;
Conference_Titel :
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
Print_ISBN :
0-7695-1825-7
DOI :
10.1109/ATS.2002.1181698
