Low power synchronous counter using improvised Conditional Capture Flip-Flop

An 8 bit synchronous counter is designed using the improvised Clock Gated Conditional Capture Flip-Flop (CGCCFF). The Conditional Capture Flip-Flop (CCFF) outputs the data, only when the input differs from the output. But, it has redundant transitions due to continuous clock flow irrespective of the input and output logic levels. The clock gating allows the clock, only when there is a need for change in output due to a change in the input. Using, the improvised CGCCFF and hence, avoiding the redundant transitions, we observe a power saving of up to 75% compared to the conventional CCFF. Moreover, it achieves a 60% higher performance than the CCFF and a better negative setup time. Hence, we implement an 8 bit synchronous counter using the CGCC flip flop. From the experimental results, we observe that, the 8 synchronous counter with CGCCFF saves 15% power than conventional CCFF counter. We simulated the results using HSPICE in 0.18μm technology.