Soft-error induced system-failure rate analysis in an SoC

This paper proposes an analytical method to assess the soft-error rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML model of the SoC and the raw soft-error rate of different parts of the platform as its inputs. Soft-errors on the design are modelled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. This Architectural Vulnerability Factor (AVF) and the raw soft-error rate of the components in the platform are used to compute the SER of cores. Furthermore, the SER and the severity of error in each core in the SoC are used to compute the System-Failure Rate (SFR) of the SoC.