Testable realizations for ESOP expressions of logic functions

Author

Zhongliang, Pan

Author_Institution

Dept. of Phys., South China Normal Univ., Guangzhou, China

fYear

2002

fDate

18-20 Nov. 2002

Firstpage

140

Lastpage

144

Abstract

A new testable design method for arbitrary logic functions is presented. The method employs AND gate arrays and XOR gate trees to realize the ESOP (EXOR-sum-of-products) expressions of logic functions. This significantly reduces the delay as compared with using cascaded XOR gates. It is shown that only n+5 test vectors are required to detect any single fault in the circuit realizations, and these tests are independent of the logic functions being realized, where n is the number of input variables. Multiple fault defects in the circuit realizations are studied, and a multiple faults test set is given. The test set can be generated easily. The method proposed in this paper is more versatile than those based on other function expression forms, since the ESOP is the most general form and it can give a small number of product terms.

Keywords

design for testability; fault location; logic arrays; logic design; logic gates; logic testing; AND gate arrays; ESOP expressions; EXOR-sum-of-products logic functions; XOR gate trees; arbitrary logic function testable design method; cascaded XOR gates; delay reduction; design for testability; fault detection; input variable number; logic function testable realizations; multiple fault detection; multiple fault test set generation; product terms; test vectors; Circuit faults; Circuit testing; Delay; Design methodology; Electrical fault detection; Fault detection; Input variables; Logic arrays; Logic functions; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1825-7

Type

conf

DOI

10.1109/ATS.2002.1181701

Filename

1181701