A low power multiplier architecture based on bypassing technique for digital filter

The objective of the paper is to present a low power 4×4 digital multiplier design to reduce power consumption of digital multiplier based on 2-dimensional bypassing method. Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. The proposed bypass cells constitute the multiplier skip redundant signal transitions when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing architecture using which we designed a Digital filter for low power dissipation in signal processing applications. Thorough post-layout simulations show that the power dissipation of the proposed 2D multiplier and FIR filter design based on 2D multiplier is reduced by more than 75% compared to the prior design with obscure cost of delay and area.