Enhanced crosstalk fault model and methodology to generate tests for arbitrary inter-core interconnect topology

Author

Sirisaengtaksin, Wichian ; Gupta, Sandeep K.

Author_Institution

Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

2002

fDate

18-20 Nov. 2002

Firstpage

163

Lastpage

169

Abstract

In this paper we develop a new fault model for capacitive crosstalk in inter-core interconnects. We also develop a framework to generate compact tests for interconnects with arbitrary topologies. Experimental results show that the proposed approach can significantly reduce test application time for large interconnects. We are in the process of extending the framework to interconnects that include tri-state as well as bi-directional nets.

Keywords

integrated circuit interconnections; integrated circuit modelling; integrated circuit testing; interference (signal); logic testing; network topology; system-on-chip; SOC arbitrary inter-core interconnect topology; bidirectional nets; capacitive crosstalk; enhanced crosstalk fault models; inter-core interconnect test generation methodology; interconnect compact test generation; system-on-chip cores; tri-state nets; Capacitance; Circuit faults; Circuit testing; Coupling circuits; Crosstalk; Design methodology; Integrated circuit interconnections; Logic testing; System-on-a-chip; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1825-7

Type

conf

DOI

10.1109/ATS.2002.1181705

Filename

1181705