DocumentCode
3212631
Title
A parallel VLSI implementation of Viterbi algorithm for accelerated word recognition
Author
Upadhyaya, Vijaykumar ; Upadhyaya, S.J. ; Kundu, Amlan
Author_Institution
Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
fYear
1993
fDate
5-6 Mar 1993
Firstpage
37
Lastpage
41
Abstract
A hardware VLSI implementation of the Viterbi algorithm is presented. The Viterbi algorithm is used to solve a word recognition problem using a hidden Markov model. In order to accelerate the speed of computation for real-time word recognition, the inherent parallelism in the recursion step of the algorithm is exploited. Details of the hardware implementation and experimental results are discussed
Keywords
Markov processes; VLSI; character recognition; parallel algorithms; Viterbi algorithm; accelerated word recognition; hardware VLSI implementation; hidden Markov model; inherent parallelism; parallel VLSI implementation; recursion step; Acceleration; Handwriting recognition; Hardware; Hidden Markov models; Parallel processing; Pipelines; Tail; Text recognition; Very large scale integration; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-3430-8
Type
conf
DOI
10.1109/GLSV.1993.224485
Filename
224485
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