Title :
C-testable systolic arrays
Author :
Faroughi, Nikrouz
Author_Institution :
Comput. Sci. Dept., California State Univ., Sacramento, CA, USA
Abstract :
A reconfigurable cell model for C-testability of systolic arrays is presented. With this model each systolic array is reconfigurable to a set of C-testable orthogonal iterative systolic arrays (OISAs). The time complexity of a systolic array is determined from the time complexity of its corresponding OISAs. The C-testable time complexities of some known systolic arrays are presented
Keywords :
VLSI; logic testing; systolic arrays; C-testability; OISAs; orthogonal iterative systolic arrays; reconfigurable cell model; systolic arrays; time complexity; Circuit faults; Circuit testing; Computer science; Integrated circuit interconnections; Pipelines; Systolic arrays;
Conference_Titel :
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-3430-8
DOI :
10.1109/GLSV.1993.224488
