• DocumentCode
    3212774
  • Title

    The disjunctive decomposition of logic functions

  • Author

    Bertacco, V. ; Damiani, M.

  • Author_Institution
    Comput. Syst. Lab., Stanford Univ., CA, USA
  • fYear
    1997
  • fDate
    9-13 Nov. 1997
  • Firstpage
    78
  • Lastpage
    82
  • Abstract
    We present an algorithm for extracting a disjunctive decomposition from the BDD representation of F. The output of the algorithm is a multiple-level netlist exposing the hierarchical decomposition structure of the function. The algorithm has theoretical quadratic complexity in the size of the input BDD. Experimentally, we were able to decompose most synthesis benchmarks in less than one second of CPU time, and to report on the decomposability of several complex ISCAS combinational benchmarks. We found the final netlist to be often close to the output of more complex dedicated optimization tools.
  • Keywords
    Boolean functions; combinational circuits; logic CAD; BDD representation; combinational benchmarks; disjunctive decomposition; logic functions; netlist; quadratic complexity; synthesis benchmarks; Logic functions;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • ISSN
    1092-3152
  • Print_ISBN
    0-8186-8200-0
  • Type

    conf

  • DOI
    10.1109/ICCAD.1997.643371
  • Filename
    643371