Stress induced degradation of 90nm node interconnects

Stress induced by thermal expansion mismatch between copper, silicon substrate and dielectrics may affect the integrity of the interconnects. As a matter of fact, the voids formed by vacancy coalescence beneath vias, are likely to induce open in the interconnects. In a view to predict the lifetime of the interconnects, we developed a predictive model of the resistance evolution due to stress induced voiding. This model is validated by experimental investigation of the resistance evolution in time of different types of via chains during isothermal annealing lasting up to 1000h.