DocumentCode
3212940
Title
Asynchronous FIFO implementation using FPGA
Author
Zhang, Yanjun ; Yi, Chunli ; Wang, Jinqi ; Zhang, Jinye
Author_Institution
Key Lab. of Instrum. Sci. & Dynamic Meas., North Univ. of China, Taiyuan, China
Volume
3
fYear
2011
fDate
29-31 July 2011
Abstract
We introduce a design of asynchronous FIFO on FPGA for the purpose of high-speed, steady data transmission between asynchronous clock domains. In the design, the memory address was organized into one ring list, using gray code as its address code, making uses of double jump technology to finish two asynchronous clock regions between address signals transmission, avoiding the meta-stability well.
Keywords
Gray codes; asynchronous circuits; field programmable gate arrays; FPGA; Gray code; address code; asynchronous FIFO implementation; asynchronous clock domains; double jump technology; steady data transmission; Clocks; Field programmable gate arrays; Radiation detectors; Reliability engineering; Semiconductor device measurement; Synchronization; FPGA; asynchronous FIFO; double jump technology; grey code;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics and Optoelectronics (ICEOE), 2011 International Conference on
Conference_Location
Dalian
Print_ISBN
978-1-61284-275-2
Type
conf
DOI
10.1109/ICEOE.2011.6013339
Filename
6013339
Link To Document