DocumentCode
3213009
Title
A SoC test strategy based on a non-scan DFT method
Author
Date, Hiroshi ; Hosokawa, Toshinori ; Muraoka, Michiaki
Author_Institution
Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan
fYear
2002
fDate
18-20 Nov. 2002
Firstpage
305
Lastpage
310
Abstract
This paper proposes a system-on-a-chip (SoC) test strategy based on a non-scan DFT method. Especially, we evaluate a basic DFT method, called NS-DFT, comparing it with a full scan DFT method. The experimental results for practical circuits and benchmark circuits demonstrate the efficiency of the NS-DFT.
Keywords
automatic test pattern generation; design for testability; high level synthesis; integrated circuit design; integrated circuit modelling; integrated circuit testing; logic design; logic testing; system-on-chip; DFT nonscan methods; NS-DFT efficiency; SoC test strategy; automatic test pattern generation; design for testability; external test ATPG; full scan DFT methods; high level design/test; system-on-a-chip; Circuit faults; Circuit testing; Computer architecture; Design automation; Design for testability; Design methodology; Energy consumption; Logic testing; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
ISSN
1081-7735
Print_ISBN
0-7695-1825-7
Type
conf
DOI
10.1109/ATS.2002.1181728
Filename
1181728
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