DocumentCode
3213057
Title
Manufacturing test of SoCs
Author
Kapur, Rohit ; Williams, T.W.
Author_Institution
Synopsys Inc., Mountain View, CA, USA
fYear
2002
fDate
18-20 Nov. 2002
Firstpage
317
Lastpage
319
Abstract
In this paper the solution the industry is driving towards for manufacturing test of SoCs is described. The quality of test for every core that is integrated on the chip is very important to the overall quality of the SoC. In this paper a method for evaluating the quality needs of an embedded core relative to the embedded environment is presented. Due to the partitioning of the test data and the increased stress in quality for individual designs the test application time is increasing. This paper presents the problems associated with test application time with SoCs.
Keywords
automatic test pattern generation; integrated circuit testing; logic testing; production testing; system-on-chip; SoCs; embedded core; embedded environment; manufacturing test; overall quality; quality of test; test application time; test data partitioning; Built-in self-test; Circuit testing; Fabrication; Integrated circuit technology; Logic testing; Manufacturing industries; Process design; Pulp manufacturing; Random access memory; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
ISSN
1081-7735
Print_ISBN
0-7695-1825-7
Type
conf
DOI
10.1109/ATS.2002.1181730
Filename
1181730
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