DocumentCode
3213120
Title
ECC algorithm and the realization of the VHDL for high-capacity solid-state storage
Author
Jiao, Xinquan ; Ma, Peijiao ; Zhang, Yuguang ; Wei, Yiran ; Ren, Yongfeng
Author_Institution
Sci. & Technol. on Electron. Test & Meas. Lab., Taiyuan, China
Volume
3
fYear
2011
fDate
29-31 July 2011
Abstract
In order to ensure the reliability of data, ECC is increasingly used in large-capacity data Nand type Flash storage. This paper describes the ECC algorithm, and designs a special error correction method for a radar recorder. The VHDL language description of the ECC algorithm is achieved and successfully embedded into the original program recorder, needs the actual data only on clock, not requires to calculate the additional timing, and occupies less system resources when running. It can correct one bit error and detect two bit errors, become an important way in data protection, and have the significant practical application value.
Keywords
error correction; flash memories; hardware description languages; radar equipment; recorders; security of data; ECC algorithm; Flash storage; VHDL language description; bit error detection; data protection; data reliability; error checking and correcting; error correction method; high-capacity solid state storage; program recorder; radar recorder; Reliability; Algorithm; ECC; Flash; VHDL;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics and Optoelectronics (ICEOE), 2011 International Conference on
Conference_Location
Dalian
Print_ISBN
978-1-61284-275-2
Type
conf
DOI
10.1109/ICEOE.2011.6013348
Filename
6013348
Link To Document