Title :
A simple wrapped core linking module for SoC test access
Author :
Song, Jaehoon ; Park, Sungju
Author_Institution :
Dept. of Comput. Sci. & Eng., Hanyang Univ., South Korea
Abstract :
For a system-on-a-chip (SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper we introduce a simple flag based wrapped core linking module (WCLM) that enables systematic integration of IEEE 1149.1 TAP´d cores and P1500 wrapped cores. Compared with other state-of-art techniques, our technique requires no modification to each core, uses less area, and provides more diverse link configurations.
Keywords :
IEEE standards; boundary scan testing; design for testability; industrial property; integrated circuit design; integrated circuit testing; logic design; logic testing; system-on-chip; DFT; IEEE 1149.1 TAP cores; P1500 wrapped cores; SoC test access; TAM; WCLM; boundary scan testing; core area requirements; design for testability; embedded reusable cores; flag based wrapped core linking modules; multiple IP cores; simple wrapped core linking modules; system-on-a-chip; systematic core integration; test access mechanisms; test access ports; test link configurations; test wrappers; Computer science; Digital signal processing; Joining processes; Logic design; Logic testing; Pins; Registers; Signal design; Switches; System testing;
Conference_Titel :
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
Print_ISBN :
0-7695-1825-7
DOI :
10.1109/ATS.2002.1181735
