Layout design dependence of NBTI for I/O p-MOSFET

Every VLSI product has some distributions of I/O p-MOSFET design with respect to the channel lengths and widths. For reliability evaluation the most vulnerable design is to be chosen. To do this there is a need to investigate a layout dependence of NBTI for I/O pMOSFET being the most weak among all others types of logic transistors. The study has resulted in the right choice of the transistors for NBTI routing testing, process optimization to improve the NBTI and to find the right spec for the product qualification.