Integrated test scheduling, test parallelization and TAM design

Author

Larsson, Erik ; Arvidsson, Klas ; Fujiwara, Hideo ; Peng, Zebo

Author_Institution

Comput. Design & Test Lab., Nara Inst. of Sci. & Technol., Ikoma, Japan

fYear

2002

fDate

18-20 Nov. 2002

Firstpage

397

Lastpage

404

Abstract

We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design to minimize the test time and the TAM routing cost while considering test conflicts and power constraints. The main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.

Keywords

VLSI; built-in self test; circuit layout CAD; design for testability; integrated circuit design; integrated circuit testing; logic testing; network routing; scheduling; system-on-chip; SoC design; SoC testing; integrated test scheduling; interconnection test; low computational cost; power constraints; scan chain partitioning; test access mechanism design; test conflicts; test parallelization; test time minimization; unwrapped cores; user-defined logic; Benchmark testing; Computational efficiency; Computer industry; Costs; Job shop scheduling; Logic testing; Power system interconnection; Power system modeling; Routing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1825-7

Type

conf

DOI

10.1109/ATS.2002.1181744

Filename

1181744