DocumentCode
3213307
Title
Core-clustering based SoC test scheduling optimization
Author
Huang, Yu ; Reddy, Sudhakar M. ; Cheng, Wu-Tung
Author_Institution
Mentor Graphics Corp., Wilsonville, OR, USA
fYear
2002
fDate
18-20 Nov. 2002
Firstpage
405
Lastpage
410
Abstract
In this paper, a method is presented to schedule tests for core-based SoCs to achieve optimal test completion time for the SoC design by simultaneously determining optimal core clustering, core cluster wrapper width, and pin mapping. For the first time the above mentioned techniques are applied concurrently to solve the SoC test scheduling problem. A heuristic algorithm implementing these techniques to determine an optimal solution is proposed.
Keywords
automatic testing; bin packing; integrated circuit testing; logic testing; optimisation; scheduling; system-on-chip; SoC test scheduling optimization; core cluster wrapper width; core-clustering based SoCs; heuristic algorithm; optimal core clustering; optimal test completion time; pin mapping; Cities and towns; Clustering algorithms; Energy consumption; Graphics; Heuristic algorithms; Job shop scheduling; Pins; Processor scheduling; Tellurium; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
ISSN
1081-7735
Print_ISBN
0-7695-1825-7
Type
conf
DOI
10.1109/ATS.2002.1181745
Filename
1181745
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