Digital circuit design for FPGA based implementation of ICA for real time Blind Signal Separation

When physically implemented, independent component analysis (ICA) algorithm can achieve a real time blind signal separation (BSS). However, due to the limited size of the hardware device in microelectronics technology, several constraints can be encountered to reach the real time processing since the application of the ICA algorithm requires the consumption of a huge number of input signal samples. Hence, the system performance was degraded since we required the processing of an important number of memory circuits with faster hardware execution time. Therefore, in order to improve the hardware performances of the device, the authors proposed the sequential processing of one neuron hardware model based on field programmable gate array (FPGA) implementation. Such approach overcomes the consumption resources and the interconnections complexities of the FPGA architecture. Thus, an optimal hardware design can be proposed in which a maximum number of samples can be handled while maintaining high speed of hardware processing time. The proposed approach was demonstrated through an experimental study of TIMIT database exhibiting a hardware execution time of 3.3 ¿s to process 10000 samples with 57 kHz of sample rates to separate two output independent signals from two input mixed signals.