Design of a quadrature clock conditioning circuit in 90-nm CMOS technology

This paper presents the operation and problems of the conventional clock conditioning circuits. A modified design is proposed to eliminate these problems and to merge two conditioning circuits together. This is to adjust and maintain two output signal properties actively during circuit operation for 4-phase 10 GHz single-ended clock signals. It is desired to have an exact 50% duty-cycle for each signal and a 90° phase difference between them. Simulation results in 90-nm CMOS technology are provided showing low output jitter.