CAD models of the input admittance of RC wires: Comparison and selection strategies

In this paper, CAD models of the input admittance of RC interconnects are discussed. To this aim, properties of RC circuits are exploited to show that the input admittance of RC wires is approximated very well by that of a low order RC circuit, as opposite to the timing modeling of RC wires. In particular, 1^st- or 2^nd-order equivalent circuits are shown to be sufficient for fast and accurate estimations of the loading effects associated with RC wires. The accuracy of these models is evaluated and compared in various practical situations that occur in automated design flows, i.e. in the evaluation of the main timing/power parameters of buffers loaded by an RC wire (e.g., delay, peak supply current, ...). This allows for understanding the suitability of each model for fast and accurate estimations of the loading effects of RC wires on buffers. Finally, a simple criterion to select the most suitable model of these loading effects is proposed for each parameter of interest in current CAD tools for VLSI design.