Placement algorithm for multiplier-based FPGA circuits

FPGA placement algorithms have stricter location constraints compared to normal ASIC placers. For large circuits, designers often start by using a best local solution and iterate until a reasonable global solution is attained, with optimization criteria such as minimum delay, area and power. This paper presents a modified greedy algorithm for placing Xilinx FPGA blocks, specifically designed for large multipliers. The solution decreases die utilization by aligning pipeline registers in an optimal way with respect to DSP48 blocks, hence decreasing delay, routing interconnect and consequently total power consumption of the design. Placement of long-integer multipliers with the proposed algorithm can result in delay reduction of up to 20%.