Digital Compensator Design to Reduce Phase Lag for Multi-Sampling Controlled DC-DC Converters

The main theme of this paper is to analyze the phase lag issue of conventional digital-controlled DC-DC converters and show the improvement using multi-sampling technique. Moreover, the compensator design for the presented multi-sampling converter is shown to further reduce the phase lag. The model which considers the effect of DPWM modulator, of digital-controlled DC-DC converter with multi-sampling technique is derived first. Then the design of three-pole two-zero compensator is presented and implemented to reduce phase lag caused by the conjugate pole pair of the plant. Experimental results are presented to confirm the reduction of phase lag.