Modeling and simulation of ΣΔ frequency synthesizers

This paper describes a very effective approach to model the ΣΔ phase noise and its effect on the closed loop VCO phase noise and spur of ΣΔ frequency synthesizers. The ΣΔ phase noise is caused by the RF divider which performs uneven divisions of the VCO output under the control of a ΣΔ calculator. The ΣΔ phase noise spectrum can be derived in a closed form by Fourier series expansion due to the periodic property of ΣΔ sequences. One way to estimate the closed loop VCO phase noise is to linearly apply the PLL transfer function to the ΣΔ phase noise spectrum. However, when the ΣΔ phase noise is not sufficiently suppressed by the loop filter, a nonlinear estimation has to be used. It was found that the spurs can be created by the nonlinearity of the VCO in conjunction with the ΣΔ phase noise, Nevertheless, the circuit nonlinearity is more dominant than the VCO nonlinearity. A performance comparison between a simulation and bench measurement of a MASH11 based synthesizer IC was performed and an excellent correlation was achieved