DocumentCode
3215320
Title
Minimum area retiming with equivalent initial states
Author
Maheshwari, N. ; Sapatnekar, S.S.
Author_Institution
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
fYear
1997
fDate
9-13 Nov. 1997
Firstpage
216
Lastpage
219
Abstract
Traditional minimum area retiming algorithms attempt to achieve their prescribed objective with no regard to maintaining the initial state of the system. This issue is important for circuits such as controllers, and our work addresses this problem. The procedure described generates bounds on the retiming variables that guarantee an equivalent initial state after retiming. A number of possible sets of bounds can be derived, and each set is used to solve a minimum area retiming problem that is set up as a 0/1 mixed integer linear program, using a new technique that models the maximal sharing of flip-flops at latch outputs. The best solution is found through enumeration of these sets, terminated on the achievement of a calculated lower bound. Experimental results show that after a small number of enumerations, optimal or near-optimal results are achievable.
Keywords
circuit optimisation; flip-flops; integer programming; linear programming; minimisation of switching nets; sequential circuits; timing; 0/1 mixed integer linear program; controller circuits; equivalent initial states; latch outputs; lower bound; maximal flip-flop sharing; memory element relocation; minimum area retiming algorithm; retiming variable bounds; sequential circuit optimization; set enumeration; Sequential logic circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-8186-8200-0
Type
conf
DOI
10.1109/ICCAD.1997.643523
Filename
643523
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