Clock-tree routing realizing a clock-schedule for semi-synchronous circuits

It is known that the clock period can be shorter than the maximum of the signal delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock schedule is given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock schedule using the Elmore delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock tree and determines the locations and sizes of intermediate buffers simultaneously. The experimental results show that this method constructs clock trees with moderate wire length compared with that of zero-skew clock trees.