DocumentCode
3215891
Title
Hierarchical partitioning for field-programmable systems
Author
Vi Chi Chan ; Lewis, D.
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
fYear
1997
fDate
9-13 Nov. 1997
Firstpage
428
Lastpage
435
Abstract
This paper presents a new recursive bipartitioning algorithm for a hierarchical field-programmable system. It draws new insights into relating the quality of the bipartitioning algorithm to circuit structures by the use of the partitioning tree (Hagen et al., 1994). The final algorithm proposed not only forms the basis for the partitioning solution of a 1-million gate field programmable system (Lewis et al., 1997) but can also be applied to general VLSI or multiple-FPGA partitioning problems.
Keywords
VLSI; field programmable gate arrays; logic CAD; logic partitioning; trees (mathematics); FPGA partitioning problems; VLSI; circuit structures; field-programmable systems; hierarchical partitioning; logic CAD; partitioning tree; quality; recursive bipartitioning algorithm; Field programmable gate arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-8186-8200-0
Type
conf
DOI
10.1109/ICCAD.1997.643571
Filename
643571
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