Title :
A 1 V, 10.4 mW low power DSP core for mobile wireless use
Author :
Shiota, T. ; Fukushi, I. ; Ohe, R. ; Shibamoto, W. ; Hamaminato, M. ; Sasagawa, R. ; Tsuchiya, A. ; Ishihara, T. ; Kawashima, S.
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
We designed a 1 V, 50 MHz, 16-bit DSP core using a 0.25-/spl mu/m Dual Vt Library, SRAM, and Mask ROM tailored for 1 V operation. The core architecture was enhanced using an alternate MAC to recover slower circuitry. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. A power simulation with a CODEC firmware showed 10.4 mW, about a quarter of a standard DSP.
Keywords :
digital signal processing chips; low-power electronics; mobile radio; radio equipment; 0.25 micron; 1 V; 10.4 mW; 16 bit; 450 ps; 50 MHz; 59 percent; CODEC firmware; MAC architecture; ROM; SRAM; dual threshold voltage technology; low power DSP core; mobile wireless communication; power simulation; voltage up-converter; Digital signal processing; Laboratories; Leakage current; Microprogramming; Random access memory; Read only memory; Regulators; Virtual colonoscopy; Voltage; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
DOI :
10.1109/VLSIC.1999.797218
