A compact 54/spl times/54-bit multiplier with improved Wallace-tree structure

Author

Itoh, N. ; Naemura, Y. ; Makino, H. ; Nakase, Y.

Author_Institution

Syst. LSI Dev. Centre, Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1999

fDate

17-19 June 1999

Firstpage

15

Lastpage

16

Abstract

As multimedia applications become popular, computers increasingly require high-speed floating point (FP) processing for three-dimension computer graphics (3DCG). Among various FP constructions, the FP multiplication is critical in both speed and area. The high-speed multiplier (MPY) frequently adopts the Wallace-tree method. However, this method requires complicated layout which increases the design cost and the chip area. We propose the new construction method of Wallace-tree which reduces the area with a simple layout. This paper describes a new method and its application to a 54/spl times/54-bit MPY design.

Keywords

floating point arithmetic; multiplying circuits; trees (mathematics); 54 bit; Wallace tree; high-speed floating point processing; multimedia computing; multiplier; three-dimensional computer graphics; Application software; Computer applications; Computer graphics; Costs; Design engineering; Large scale integration; Layout; Multimedia systems; Pipelines; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-95-6

Type

conf

DOI

10.1109/VLSIC.1999.797219

Filename

797219