• DocumentCode
    3216280
  • Title

    Simulated quenching: a new placement method for module generation

  • Author

    Sato, S.

  • Author_Institution
    Fujitsu Labs. Ltd., Kanagawa, Japan
  • fYear
    1997
  • fDate
    9-13 Nov. 1997
  • Firstpage
    538
  • Lastpage
    541
  • Abstract
    This paper addresses a placement method for module generation. The conventional partitioning based method can not guarantee the best results in consecutive partitioning. Also, when the size of the cells varies greatly, it can be too strong a constraint for minimum partitioning under "partitioning into two similar size subcircuits". Although the conventional simulated annealing (SA) based method gives a better result, it requires extremely long computation time. This paper proposes an algorithm based on SA method which employs the divide and conquer technique to give better results than partitioning based method and to give a much faster computation time than SA method. We applied this idea to linear placement. It was found that the total wiring length was improved by about 10% compared to that of the spectral method (previously recognized to be the best). The computation time was greatly reduced from the SA method.
  • Keywords
    VLSI; circuit layout CAD; computational complexity; divide and conquer methods; simulated annealing; VLSI chips; computation time; consecutive partitioning; design automation; divide and conquer technique; gate array design; module generation; partitioning based method; placement method; simulated annealing; simulated quenching; spectral method; total wiring length; Simulated annealing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • ISSN
    1092-3152
  • Print_ISBN
    0-8186-8200-0
  • Type

    conf

  • DOI
    10.1109/ICCAD.1997.643591
  • Filename
    643591