DocumentCode
3216306
Title
A 1 Gbps transceiver with receiver-end deskewing capability using non-uniform tracked oversampling and a 250-750 MHz four-phase DLL
Author
Yongsam Moon ; Deog-Kyoon Jeong
Author_Institution
Seoul Nat. Univ., South Korea
fYear
1999
fDate
17-19 June 1999
Firstpage
47
Lastpage
48
Abstract
This paper describes a low power, 1 Gbps, CMOS link with measured bit error rate (BER)<10/sup -14/. To obtain the low BER, skew between clock and data is detected and removed by using non-uniform tracked over-sampling technique with a high-resolution phase control. A delay-locked loop (DLL) with a wide operating frequency range of 250-750 MHz generates four phase sampling clocks.
Keywords
CMOS digital integrated circuits; delay lock loops; low-power electronics; signal sampling; transceivers; 1 Gbit/s; 250 to 750 MHz; CMOS transceiver; bit error rate; four-phase delay-locked loop; low-power design; nonuniform tracked oversampling; phase control; phase sampling clock; receiver-end deskewing; Bit error rate; Clocks; Delay lines; Jitter; Phase control; Phase detection; Phase locked loops; Sampling methods; Transceivers; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-930813-95-6
Type
conf
DOI
10.1109/VLSIC.1999.797231
Filename
797231
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