Title :
On L-band double loop, fractional-N digital synthesizer
Author :
Oka, Seigo ; Wang, Thomas N C
Author_Institution :
Systec Reseasrch Inc., Sagamihara City, Japan
Abstract :
Using a double PLL loop approach together with a deferential-cyclic-fractional-N design, we have developed a L-band digital frequency synthesizer to achieve SSB noise as low as -75 dBc/Hz at 100 Hz offset, step size at 12.5 kHz and a lock-up time at 500 μs maximum
Keywords :
UHF circuits; digital phase locked loops; frequency synthesizers; radio equipment; L-band; SSB noise; double PLL loop; fractional-N digital synthesizer; frequency synthesizer; Amplitude modulation; Bandwidth; Detectors; Frequency synthesizers; L-band; Phase detection; Phase locked loops; Phase noise; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Microwave Conference Proceedings, 1997. APMC '97, 1997 Asia-Pacific
Print_ISBN :
962-442-117-X
DOI :
10.1109/APMC.1997.659369
