DocumentCode
3216324
Title
GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link
Author
Ellersick, W. ; Chih-Kong Ken Yang ; Horowitz, M. ; Dally, W.
Author_Institution
Comput. Syst. Lab., Stanford Univ., CA, USA
fYear
1999
fDate
17-19 June 1999
Firstpage
49
Lastpage
52
Abstract
A 4-bit 12-GSample/sec A/D converter (GAD) has been fabricated in a 0.25-/spl mu/m CMOS process to investigate the design of an equalized multi-level link. Clocked differential amplifiers were used to sample the input, followed by high-speed comparators with current-summed offset cancellation. Input bandwidth was measured at 2.5 GHz. Eight 1.5-GSample/sec flash A/D converters were interleaved to achieve the aggregate sample rate.
Keywords
CMOS integrated circuits; analogue-digital conversion; equalisers; high-speed integrated circuits; 0.25 micron; 2.5 GHz; 4 bit; CMOS flash A/D converter; GAD; current-summed offset cancellation; differential amplifier; equalized multi-level link; high-speed comparator; input bandwidth; sample rate; Bandwidth; CMOS process; Circuits; Clocks; Error correction; Latches; Parasitic capacitance; Sampling methods; Signal design; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-930813-95-6
Type
conf
DOI
10.1109/VLSIC.1999.797232
Filename
797232
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