Title :
Technical trends of LSI packaging: recent advances in CSPs and high density substrates
Author :
Wakabayashi, S. ; Shimizu, M.
Author_Institution :
Div. of Res. & Dev., Shinko Electr. Ind. Co. Ltd., Japan
Abstract :
The use of CSPs, Direct Flip Chip Attach and high density substrate should bring tremendous benefits for electronic devices in terms of performance, speed, weight, real estate and cost saving. Several CSPs are already applied for actual mobile electronic devices. Among these CSPs, Super CSP is a newly developed CSP which processed all packaging processes in a wafer form. MOST (Micro Spring On Silicon Technology) is another wafer level packaging technology which has many micro springs on a wafer for board attach. The micro springs were formed by existing wire bonding technology which uses specially designed tool motion. These two CSPs are produced by common rerouting technology with flip chip bumping, i.e. thin film and plating technologies. The structures and manufacturing processes are described and reliability of the CSPs and bumps on wafers are proved as satisfactory for actual application. High density substrates and packages are another important parts for high performance devices and modules. Newly developed high density buildup substrate using polymer coated copper sheets and related technologies such as via filling with copper plating and pre-soldering technology for flip chip attach are described. The reliability of the substrate and flip chip bonding technology are also confirmed.
Keywords :
VLSI; chip scale packaging; copper; flip-chip devices; integrated circuit packaging; integrated circuit reliability; large scale integration; lead bonding; microassembling; substrates; CSP; Cu; Cu plating; LSI packaging; Si; VLSI packaging; direct flip chip attach; flip chip bonding technology; flip chip bumping; high density substrates; manufacturing processes; micro spring on silicon technology; polymer coated Cu sheets; presoldering technology; reliability; rerouting technology; via filling; wafer level packaging technology; wire bonding technology; Chip scale packaging; Copper; Costs; Electronics packaging; Flip chip; Large scale integration; Polymer films; Springs; Substrates; Wafer scale integration;
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
DOI :
10.1109/VLSIC.1999.797239