A programmable processing element dedicated as building block for a large area integrated multiprocessor system

Author

Hermann, K. ; Hilgenstock, Jörg ; Gaedke, Klaus ; Jeschke, Hartwig ; Pirsch, Peter

Author_Institution

Lab. fur Informationstechnol., Hannover Univ., Germany

fYear

1996

fDate

9-11 Oct 1996

Firstpage

98

Lastpage

103

Abstract

The architecture and implementation of a programmable processing element dedicated as building block for a large area integrated multiprocessor system is presented. The processor element allows an efficient implementation of video coding standards. It consists of a RISC processor supplemented by a low level coprocessor for computation intensive convolution-like tasks. Several of the processing elements can be bus-connected to built a coarse-grained MIMD based large area integrated multiprocessor system. Each of the processor elements provides high performance for video coding tasks in order to keep the overall number of required processing elements for complex real-time video coding applications small. A key feature of the processing element to support large area integration is a unidirectional data supply which allows reconfiguration strategies for the interconnection network. Furthermore on-chip program and data memories have been implemented in order to relax the overall bandwidth requirements of the large area integrated multiprocessor system

Keywords

CMOS digital integrated circuits; coprocessors; digital signal processing chips; multiprocessing systems; parallel architectures; real-time systems; reduced instruction set computing; video codecs; video coding; CMOS DSP chip; RISC processor; architecture; building block; coarse-grained MIMD; interconnection network; large area integrated multiprocessor system; low level coprocessor; onchip data memories; onchip program memories; programmable processing element; real-time codecs; real-time coding applications; reconfiguration strategies; unidirectional data supply; video coding standards; Circuits; Computer architecture; Convolutional codes; Coprocessors; Laboratories; Multiprocessing systems; Multiprocessor interconnection networks; Reduced instruction set computing; System-on-a-chip; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-2204

Print_ISBN

0-7803-3639-9

Type

conf

DOI

10.1109/ICISS.1996.552416

Filename

552416