Title :
A 12.4 mW CMOS front-end for a 5 GHz wireless-LAN receiver
Author :
Samavati, H. ; Rategh, H.R. ; Lee, T.H.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
This paper presents a 12.4 mW front-end for a 5 GHz wireless-LAN receiver fabricated in a 0.24 /spl mu/m CMOS technology. It consists of an LNA, mixers and an automatically tuned third-order filter controlled by a low-power PLL. The filter attenuates the image-signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm.
Keywords :
CMOS analogue integrated circuits; MMIC amplifiers; MMIC mixers; active filters; field effect MMIC; low-power electronics; phase locked loops; radio receivers; wireless LAN; 0.24 micron; 12.4 mW; 4.8 dB; 5 GHz; 5.2 dB; LNA; LNA/filter combination; automatically tuned filter; cascode devices; image-signal attenuation; low power CMOS front-end; low-power PLL; mixers; third-order filter; wireless-LAN receiver; CMOS technology; FCC; Filters; Noise figure; Phase locked loops; Radio frequency; Radio spectrum management; Signal to noise ratio; Voltage-controlled oscillators; Wireless LAN;
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
DOI :
10.1109/VLSIC.1999.797245
