A robust 8F/sup 2/ ferroelectric RAM cell with depletion device (DeFeRAM)

Author

Braun, G. ; Hoenigschmid, H. ; Schlager, T. ; Weber, W.

Author_Institution

Siemens Corp. Technol., Munich, Germany

fYear

1999

fDate

17-19 June 1999

Firstpage

99

Lastpage

102

Abstract

This paper describes an area penalty free, leakage compensated and noise immune 8F/sup 2/ cell design suitable for high density low power FeRAM generations. The array concept features a 1TIC ferroelectric memory cell containing an additional depletion device (DeFeRAM) controlled by the passing word line in a folded bit line architecture. A highly reliable three level word line driver circuit design is discussed.

Keywords

cellular arrays; compensation; driver circuits; ferroelectric capacitors; ferroelectric storage; integrated circuit noise; integrated memory circuits; leakage currents; low-power electronics; random-access storage; 1TIC ferroelectric memory cell; area penalty free cell design; depletion device; folded bit line architecture; high density FRAM; highly reliable word line driver circuit; leakage compensated cell design; low power FeRAM; noise immune 8F/sup 2/ cell design; robust ferroelectric RAM cell; three level word line driver circuit design; Capacitors; Circuits; Ferroelectric films; Ferroelectric materials; Leakage current; Nonvolatile memory; Random access memory; Robustness; Threshold voltage; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-95-6

Type

conf

DOI

10.1109/VLSIC.1999.797250

Filename

797250