DocumentCode :
3216769
Title :
Interconnect layout optimization under higher-order RLC model
Author :
Cong, J. ; Cheng-Kok Koh
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fYear :
1997
fDate :
9-13 Nov. 1997
Firstpage :
713
Lastpage :
720
Abstract :
Studies the interconnect layout optimization problem under a higher-order RLC model to optimize not just the delay but also the waveform for RLC circuits with non-monotone signal response. We propose a unified approach that considers topology optimization, wire-sizing optimization and waveform optimization simultaneously. Our algorithm considers a large class of routing topologies, ranging from shortest-path Steiner trees to bounded-radius Steiner trees and Steiner routings. We construct a set of required-arrival-time Steiner (RATS) trees, providing a smooth trade-off among signal delay, waveform and routing area. Using a new incremental moment computation algorithm, we interleave topology construction with moment computation to facilitate accurate delay calculation and evaluation of waveform quality. Experimental results show that our algorithm is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot and routing cost.
Keywords :
circuit layout CAD; circuit optimisation; delays; network routing; network topology; signal synthesis; trees (mathematics); waveform analysis; RATS trees; Steiner routings; bounded-radius Steiner trees; delay optimization; higher-order RLC model; incremental moment computation algorithm; interconnect layout optimization; nonmonotone signal response; required-arrival-time Steiner trees; resistance-inductance-capacitance circuits; routing area; routing cost; routing topologies; shortest-path Steiner trees; signal delay; signal settling time; topology optimization; voltage overshoot; waveform optimization; waveform quality evaluation; wire-sizing optimization; RLC circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-8186-8200-0
Type :
conf
DOI :
10.1109/ICCAD.1997.643617
Filename :
643617
Link To Document :
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