A 5 GHz, 32 mW CMOS frequency synthesizer with an injection locked frequency divider

Author

Rategh, H.R. ; Samavati, H. ; Lee, T.H.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1999

fDate

17-19 June 1999

Firstpage

113

Lastpage

116

Abstract

A fully integrated 5 GHz phase locked loop- (PLL-) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. A voltage-controlled differential injection-locked frequency divider (VCDILFD) is used as the first frequency divider in the PLL feedback loop to reduce power consumption and eliminate the need for an off-chip frequency divider. The total synthesizer power consumption is 32 mW. The phase noise is measured to be -101 dBc/Hz at 1 MHz offset frequency. The PLL bandwidth is 300 kHz and the measured spurious level at the adjacent channel is less than -54 dBc.

Keywords

CMOS integrated circuits; frequency dividers; frequency synthesizers; mixed analogue-digital integrated circuits; phase locked loops; phase noise; very high speed integrated circuits; 0.24 micron; 300 kHz; 32 mW; 5 GHz; CMOS frequency synthesizer; PLL feedback loop; PLL-based frequency synthesizer; VCO; injection locked frequency divider; phase locked loop synthesizer; phase noise; power consumption; prescaler; voltage-controlled differential divider; CMOS technology; Energy consumption; Feedback loop; Frequency conversion; Frequency measurement; Frequency synthesizers; Noise measurement; Phase locked loops; Phase noise; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-95-6

Type

conf

DOI

10.1109/VLSIC.1999.797255

Filename

797255