Title :
A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4 Gb DRAM´s
Author :
Hoenigschmid, H. ; Frey, A. ; DeBrosse, J. ; Kirihata, T. ; Mueller, G. ; Daniel, G. ; Frankowsky, G. ; Guay, K. ; Hanson, D. ; Hsu, L. ; Ji, B. ; Netis, D. ; Panaroni, S. ; Radens, C. ; Reith, A. ; Storaska, D. ; Terletzki, H. ; Weinfurtner, O. ; Alsmeie
Author_Institution :
Siemens Microelectron., IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA
Abstract :
A 7F/sup 2/ DRAM cell and corresponding vertically folded bitline architecture has been fabricated using a 0.175 /spl mu/m CMOS technology. This concept features an advanced 30/spl deg/ tilted array device layout and an area penalty free inter BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals.
Keywords :
CMOS memory circuits; DRAM chips; integrated circuit layout; integrated circuit noise; memory architecture; 0.175 micron; 4 Gbit; 7F/sup 2/ DRAM cell; CMOS DRAM; CMOS technology; bitline twists; dynamic RAM; local well noise minimisation; penalty-free vertical BL twists; tilted array device layout; twisting intervals; vertically folded bitline architecture; Decoding; Random access memory; Solid state circuits; Very large scale integration;
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
DOI :
10.1109/VLSIC.1999.797259
